Semiconductor

At this stage an RTL designer writes the rtl code based on design specification, particularly either in Verilog and vhdl languages as they are technology independent.

Behavioral functionality of the design is verified using tools like synopsys VCS, Questasim,Xilinx vivado correctly at this stage. Performs code coverage test with the use of test vectors. Code coverage include branch coverage, statement coverage, toggle coverage and expression coverage using functional and timing simulation tools.

Converts rtl code into gate level representation using tools like Design complier-sysnopsis, genus- cadence or leanardo spectrum-mentor graphics

Contains only module instantiations and these modules are standard cells like AND/NAND/NOR/OR

Goes for logical functionality check in gate level using tools like Formality -Synopsis, conformal – Cadence, QuestaSLEC- Mentor Graphics At thi stage , the model undergoes DFT- Design for Test. DFT is a technique, which facilitates a design to develop into testable after fabrication. we put along with the design logic along with 'Extra' logic during completion process, which helps post-production testing. Post-production testing is essential because, the process of manufacturing is not 100% error free. It includes

✎  Scan path design

✎  Bist(memory and digital logic)

Placemnt and routing using tools like Innocus- cedence, IC Compiler- synopsis, Olympus SOC- Mentor graphics are performed at his stage.It includes: block placement, design portioning, pin placement, and power optimization.

Clock tree synthesis is a method of building the clock tree and meeting the definite timing, area and power necessities. It helps in providing the clock association to the clock pin of a sequential element in the essential time and area, with low power utilization.

In order to evade high power utilization, amplify in delays and a vast number of transitions, certain structures can be used for optimizing CTS structure such as H-Tree Structure, Mesh Structure, X-Tree Structure, Hybrid structure and Fishbone Structure.

After steering, ASIC design layout undergo three steps of physical verification, known as signoff checks. This phase helps to check whether the layout operational the way it was designed to. The subsequent checks are followed to avoid any error just before the tape out:

✎Layout versus schematic (LVS) is a method of inspection that the geometry/layout match the schematic/net list.

✎Design rule checks (DRC) is the method of inspection that the geometry in the GDS file follows the rules given by the foundry

✎Logical equivalence checks (LVC) is the method of equivalence check between pre and post design layout.

Stands for Graphical Data Stream Information Interchange .Format in which the final model is send to foundry

In the Final stage of the tape out, the engineer perform wafer processing, packaging, testing, verification and delivery to the physical IC. GDSII is the file created and used by the semiconductor foundries to fabricate the silicon and handled to client.